High performance graphics processing commonly requires a specialized graphics frame buffer including a graphics engine in communication with a host processor over a bus. Control over a graphics frame buffer of this sort has been achieved by a variety of means, typically involving hardware configured to supervise the operation of the graphics engine. The graphics engine is typically controlled through commands from a host computer's processor over a bus so as to provide request code and data from the host processor to the graphics engine. High-performance frame buffers in the prior art have three general characteristics.
First, the video board logic for performing texture processing, i.e. the integrated circuit that performs those functions, is separate from the circuitry for performing other frame buffer manipulations, such as graphics display requests. This results in limitations placed upon the performance of the graphics system due to the frame buffer designer's having to arrange for a communication path between the texture processor and other components on the board.
Second, prior art video frame buffers arrange video memory in a linear fashion, such that consecutive memory locations represent the next pixel upon a given row of the display. In effect, prior art video memory arrangements track the scanline of the display.
Third, prior art video frame buffers store as one word in memory all information relevant to a particular display pixel. Consequently, acquiring the color value information for displaying a row of pixels upon the display requires skipping through video memory to obtain the values. This can be a very inefficient process.
Prior art video frame buffers, exemplified by the Edge III graphics processing system sold by Intergraph Corporation, and described in a technical white paper titled GLZ5 Hardware User's Guide, which is incorporated herein by reference, represents the state of the prior art in graphics processing systems. However, the Edge III, as do other prior art video buffers, suffers from the three general limitations referenced above: lack of integration, linear video buffer memory, and consecutive placement of pixel information within the frame buffer. These limitations result in a graphics processing system that is not as efficient or speedy as it could be. The present invention resolves these issues.